Falstad Circuit Simulator and the SR Latch

Summary

In my last post I described a logic circuit simulator that I was working on.  I have continued to work on this simulator source code and have discovered a difficulty in simulating a flip-flop.  While researching for a creative solution to my dilemma I stumbled across a circuit called a Falstad circuit.  This circuit demonstrates the output glitch that I discovered in my last article in a rather interesting way.

The Circuit

So the circuit is extremely simple.  One AND gate with two inputs and an inverter:

falstad_circuit

If you remember your digital logic circuitry, you’ll recognize that an AND gate is only true when both inputs are true.  Since there is an inverter between the two inputs of the AND gate, then any input will produce a true and false or a false and true input to the AND gate.  So the output will always be false.

That’s exactly how this circuit behaves in a perfect world:

falstad_perfect

Great circuit.  It basically does nothing.  That would be a perfect circuit with no delays.  However, in the real world there are delays.  The inverter will have a delay and the output of the inverter will be true for a few nanoseconds before the input of true is transmitted out as a false.  That means that the AND gate will get a short duration true output.  So let’s change the delay to a standard TTL gate delay for this circuit and re-run the simulation:

falstad_normal_ttl

The output of the AND gate is also delayed, so it appears in the graph above that the true for the AND gate occurs right after the red line goes red.

Latches

Latches were designed to avoid the delay problem that I’m demonstrating with the Falstad circuit above.  The idea of a latch is that it will only accept the input and latch it in place.  The simplest latch is the Set-Reset or SR latch:

sr_latch

What this circuit does is hold the output when the inputs are both true.  If the S input receives a false pulse, then Q will go high and Q-bar will go low and the configuration will hold this value until R receives a pulse.  So the circuit should behave something like this:

sr_sample

I’m only showing the S input and assuming the R input stays true or high for the entire signal above.  I’m also only showing the Q output since Q-bar will be the opposite.

I had to make a couple of changes to my circuit simulator to make this work.  First, I changed the RunCircuit() method to run the whole circuit for sample 0, then run the circuit for the next sample until all samples were completed.  My previous algorithm ran all the samples for an output, then did the next output until the circuit was complete.  The second change involved the computation for the output of the circuit for one sample.  I had to check and see if the number of samples available on an input was one less than the sample being worked on.  If that was the case, then I just take the previous sample since the output of one of NAND gates will not arrive at the input of the other until the circuit completes.  Therefore, I just lookup the previous level.  This is my output from the simulator (with a perfect circuit):

simulator_sr_latch

As you can see Q goes high when S goes low.  Q then remains high no matter what S does afterward.

Before I figured out how to make my simulator work, I was unsure of my results so I dragged out the breadboard and dug around in my bag of chips (oh, you think I’m kidding):

bag_o_chips

Anyway, I needed a TTL 7400 NAND gate and I knew there was at least one in this bag.  So I found one and stuck it in my breadboard and wired a SR latch:

sr_latch_circuit2

Yup, it worked as I remembered it working.

Next, I changed my TTL logic to use normal logic with delays.  Yikes.  That was not so pretty.  I tweaked the algorithm a little to read the last input that was sampled when there are not enough input samples.  That helped, but I still get a bounce issue and apparently, that’s a problem in real flip-flops.

sr_latch_ttl_normal

Once the SR latch is triggered by S going low, then the arrangement becomes stable.  The width of that oscillation is the delay time of one NAND gate.  This is occurring when both S and R are high at the same time.   This is supposed to be the “invalid” condition according to the truth table:

sr_latch_truth

Apparently, the simulator is correct.  My next project will be the JK Flip-Flop.  If you’re hungry for more information on the subject this is a very nice article about Latches: http://www.electronics-tutorials.ws/sequential/seq_1.html.

Where to get the Code

You can go to my GitHub account and download the full source code by clicking here.  This is a work in progress, so expect changes in the future.

 

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