JK Flip Flop Simulator

Introduction

I’ve been working on a simulation of the JK flip flop for quite some time now.  I had to tweak my algorithms a bit to overcome problems with an unstable condition that I’ll discuss in this blog post.

 

Handling Unknown Inputs

One of the problems with circuits that contain feed back connections is that there is an unknown startup state.  In the world of electronics, imperfections in the transistor circuit will cause the condition to be a one or a zero almost immediately.  If all transistors were perfect a race condition can occur and in fact, many circuits experience race conditions for a short period as the circuit stabilizes.

As I thought deeper about unknown inputs I decided that the output of a gate can still be known if some of it’s inputs are unknown.  For example, and AND gate needs all inputs to be a true in order for the output to be a true.  So in that instance, all inputs need to be known for the output to be a true.  For a false output to occur, only one input needs to be false.  This also means that if one or more inputs are false, then unknown inputs don’t matter, because we know the output will be false.  Here’s the logic table for a 3-input AND gate:

3inputnand

You’ll notice that only one combination requires all the inputs to be known in order to get a known output.  With this knowledge, we can propagate signals through a circuit by ignoring unknown inputs until we hit a wall where we can’t predict the output of one or more gates.  The NAND gate is identical to AND except for the output.  For an OR gate, we can predict the output depending on one or more true inputs, all inputs must be false in order to get a false output:

3inputor

The inverter has no equivalent.  The input must be known for the output to be known.  The same for the exclusive OR gate.

 

The JK Circuit

Here’s the JK Flip Flop circuit (and logic table) that I constructed virtually using NAND gate:

jkff

In order to test the circuit, I started with perfect TTL NAND gates (no delay) and ran the circuit.  This produced a problem where I had an unknown circuit path.  At first, I propagated all the inputs right up to the gate inputs (red wires represent a 5 input or a true condition, black wires are uknown):

jkff_01

This created a problem where gates 3 and 4 cannot propagate the signal any further.  Their inputs are basically a true, true and unknown.  So I decided to propagate a circuit as a zero when this condition occurs.  I represented the zero as a blue line:

jkff_02

That seems to take care of the log jam because now, we can compute NAND gate 3 as a true output, and we can compute gate 1 as a true output, etc, until we get this condition:

jkff_03

Now you can see that the circuit is invalid.  Gate 2 should have a true output.  So this is an unstable starting condition.

 

Setting the Latch

Next, I tried to start the circuit with J false and K true, clock starts at true.  I end up with this circuit condition:

jkff_04

Initially, gate 4 has all three true inputs if gate 1 is producing a true output.  That will cause gate 4 to go false and gate 2 will output a true.  Gate 3 is forced to have a true output because J is false, therefore gate 1 will have two true inputs and a false output.  This causes gate 4 to turn back off or produce a true.  But this is a stable latch condition.

The reset operation is the same:

jkff_05

 

The Toggle State

For the perfect circuit, the toggle state, as shown earlier is unstable and this is the output from the simulator:

jk_perfect_toggle

The Q Bar output will not stabilize and always returns to the true state.  When I set the gates to normal TTL delay and adjust the clock to 5 ns (shorter than the delay) the instability is obvious:

jk_normal_toggle_short_clk

With a longer clock (20 ns):

jk_normal_toggle_long_clk

 

Conclusion

I’m going to run with this circuit emulation for now.  I have a choice to make, allow one or more gates to have an invalid output given it’s inputs, or allow an invalid wire to exist (where it has 5 volts at one end and zero at the other).  Either situation is not normal and this circuit is known to have a stability problem when starting up.  What I’m going to do next is wire up a virtual JK Master/Slave flip-flop.  This circuit fixes the inherent instability of the JK circuit.  I’ll show how that circuit works in my next post.

 

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