JK Master/Slave Flip Flop

Introduction

I’m sure readers are becoming bored with Flip Flops by now, but bear with me.  The previous JK flip flop was a simple 4-NAND gate device, this circuit is the standard two flip flop device that is more stable when used in toggle mode.

The Circuit

The Master/Slave flip flop circuit is a bit more complex:

master_slave_circuit

The basic idea of this circuit is to latch the data into the first flop flop, then transfer to the second flip flop when the clock goes from high to low.  The truth table for this flop flop is the same as the JK flip flop demonstrated in my last blog post:

jk_flip_flop_truth_table

When this circuit is executed with perfect logic gates, the following signal is generated:

jk_master_slave_perfect

As you can see the Q and Q-bar outputs change states or “toggle” when the clock signal goes from a high to a low.  This circuit assumes that the logic gates have no delay.  For a circuit using normal TTL delay times, this is the generated output:

jk_master_slave_normal

The delay from the clock transition to the Q and Q-bar is quite pronounced.  In fact the output isn’t switched until after the signal goes back high again.  Let’s slow the clock speed down to make sure that the Q and Q-bar are switching on the falling edge transition.  The above diagram uses a 20ns clock timing, the diagram below uses 40ns:

jk_master_slave_normal_40ns

That pretty much verifies that the Q and Q-bar are triggered from the falling edge of the clock.  Notice how Q-Bar is out of sync with Q.  That’s due to the cross-wiring between the two.  There is a delay that occurs in gate 1 to gate 2 and there’s a delay from gate 5 to 6 and vice versa.

Purpose

The purpose of this software and the whole exercise of verifying the behavior is to build a simulator that can simulate a digital circuit as close to the real circuit as possible.  My next task will be to make it possible to create modules of circuits and then wire them together to run everything as one large circuit.  With the basic 1-bit full adder circuit, I should be able to put multiple instances of the full-adder into an 4-bit adder circuit and emulate the TTL 7483.  Adding TTL circuits to my toolbox will allow me to build a real device out of TTL chips and just simulate how it should work in real life.  Of course, real-life doesn’t work exactly like a simulator.  There are factors that I still have not accounted for.  Such as the difference in delay of a falling edge signal verses a rising edge signal or maximum fan-out capacity.  Once I get to this point, I’m going to start building the real circuit to verify that the signals match.

If you’re interested in learning about the TTL circuits that are on the market, you can go to the wiki page here.

Where to get the latest code

You can download the latest copy at my GitHub account by clicking here.

 

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