The ALU

Summary

I’ve added the 74181 ALU TTL circuit to my logic simulator.  This blog post will discuss the differences between this ALU and the 74381 that I discussed about in a previous blog post.

The 74381

I added the 74381 ALU (Arithmetic Logic Unit) circuit to the logic simulator a few weeks ago and then I decided to build some real circuits to experiment with.  I mentioned in my previous blog post that the 74381 was not available for purchase (at least I haven’t found a supplier yet).  I decided to add the 74181 circuit to the emulator.  This circuit has a few quirks.  First, there are two truth tables in my logic book: Active High Data and Active Low Data.  The same circuit can be represented as though the outputs are inverted or not.  The difference is that the logic functions that are used are in a different order in the logic table.  For instance: In the active high version the A plus B function is activated by S0-S3 equal to H,L,L,H and the carry in must be H.  In the active low version, the s0-s3 are identical but the carry in must be L.  For the F = 0 function in active high, S0-S3 must equal L,L,H,H and M equals H.  For active low S0-S3 must equal H,H,L,L and M equals H.  Oh what fun.  So I chose the active high table and just setup my unit tests to assume that the outputs match that setup.  The fact that this chip can represent active high or active low means that there are 4 select bits or what seems like 16 functions.  However, there are functions in active high that are useless because the selector is used for active low functions.

The functions that are supported by the 74381 are also on the 74181:

  • Clear
  • B – A
  • A – B
  • A plus B
  • A + B (OR)
  • AB (AND)
  • A xor B
  • Preset (all 1’s)

The 74181 also supports not A, not B and A = B.
Here’s the circuit for the 74181 (click to see full sized image):

ttl_74181

I had a lot of fun creating that circuit in Visio.  I opted to create gate 57 as a special negated input OR gate instead of using two inverters on the input.  I’m only testing this circuit with the “perfect” TTL circuit.  I might have to do some fancy foot-work to make the timing come out right for the real circuit.  My point in mentioning this is that the reason why gates are represented with negated inputs instead of showing two inverters is that the circuit inside the chip is created with transistors and it was designed as a special negative input OR gate to cut the delay time.  If an additional transistor is used on each input as inverters, then the circuit path for gate 57 will be slower.  It appears that this circuit was designed to equalize the delay time from the inputs (a0-a3 and b0-b3) to the inputs (f0-f3) and to reduce any transients that can occur if one path is longer than another.  Although the inverter on b0-b3 probably causes a delay between the a and b inputs.  As you can see by the next diagram there are 7 levels of gates that a signal must pass through (no feed back paths):

ttl74181_critical_pathGates 34 through 36 appear to be behind the row of AND/NAND gates in zone 4, but they are at the same level of circuitry.  No signal goes from level 4 to level 5 without passing through a gate.  There is even a one-input NAND gate to ensure that the signal delay through gate 37 is equal to all other signals arriving at gate 53.

One thing I discovered while researching ALUs is that this circuit shows up in a lot of class exercises for electronic engineering classes.  I’ve found some pretty good power point slides showing the basics of half and full adders up to the 74181 circuit itself.

Here’s some history of the 74181 that explains why it’s so popular: http://apollo181.wixsite.com/apollo181/about.  The 74181 also has it’s own Wiki: https://en.wikipedia.org/wiki/74181.  One thing to note is that there are two circuits shown for this chip.  The TTL logic book has the circuit that I translated into Visio above and many of the on-line references, including the wiki page, show a slightly different circuit.  When you look at the circuit diagram in the Wiki article you’ll see an AND gate and an inverter instead of an XOR gate.  This is not a direct substitution as you can see from this:

xor_vs_and_inverter

I have not investigated the reason for this difference and it could be a correct circuit with a difference in the selection of the functions used by the chip.  I also stumbled across a data sheet for a Motorola brand 74181 and it had a wiring mistake on the circuit diagram:

motorola_datasheet_mistakeConnecting two inputs to the same wire would be a short-circuit.  If you go to the Wiki article you’ll notice that the M wire should be inverted and should connect to the other wire of the NAND gate at the bottom.  The Cn wire should connect directly to the NAND gate where it currently connects (after the inverter).

The circuit above came from my Logic Databook, which was published by National Semiconductor in 1981.  That circuit works correctly according to the unit tests that I setup (using the Active High Data truth table).

Where to get the Code

You can go to my GitHub account to get the latest and greatest code (click here).  This project is still in the research phase so there will be changes coming.  You can get the specific version of this code for this article by downloading this version: (click here).

 

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