Generic Array Logic Hexadecimal Display

I’ve always wanted a decoder that did more than the TTL 7447 BCD to seven segment display decoder did.  I wanted the full hexadecimal output.  One of my first real projects for the GAL was to create such a chip.  I have an old PAL databook that was published by National Semiconductor in 1982.  I pulled the book off my shelf, just to see what information was in it and to my surprise was a hex display “Application suggestion”.  What luck!  Here’s a picture of the page in the book (click for larger image):

What I didn’t realize when I started this project was that it was going to be a real learning experience.  At first, the chip did not produce any outputs at all.  Then I had issues with several of the segments lighting all the time.  Typing the data into the JEDEC file was tedious and verifying that the fuses were correct was more tedious.  The first problems I found were due to my translation to the .JED file.  I expected that to occur, so I went over the file several times in detail.  Once I determined that I typed it in as it was shown in the book, I began to suspect that the book was wrong (that turned out to be an understatement).

I found a few typos in the diagram above.  First, the PTD fuses were not all correct.  There’s a pattern that they followed when the fuses were set and I noticed that some of the PTD fuses (the “X”s on the AND gates to the right side of the diagram) were not “X”d when the row was empty.  I fixed those and obtained some results.

In order to fix the segment problems I took a look at these two pages:

The page on top is the design page with PALASM logic formulas.  The bottom page is the segment diagram showing which segments will light up given a set of inputs D0-D3.  Both diagrams have mistakes.  I printed a bunch of segment display diagrams so I could work out the logic formulas and determine which formula would cause each segment to light up.  That appeared to be the way the fuses were laid out in the chip.  I focused on the D segment first:

The logic formula for the D segment was listed as follows (ignoring the RBO and LT lines):

/D = /D1*D3 + /D0*/D2*/D3 + D0*D1*/D2 + /D0*D1*D2 + D0*/D1*D2

What this translates to is that the D output (inverted) will be equal to the not D1 AND D3, or the not D0 AND not D2 AND not D3, etc.  As you can tell by my hand writing the /D1*D3 causes all the D segments to light for the binary combinations where D1 is zero and D3 is a one.  I wrote a 25 next to each of those because this logic is used on line 25 of the fuse map.  Unfortunately, this combination occurs for 1001, which should be segments ABCFG (no D segment).  To fix this, I added a /D0 to the equation:

/D = /D1*D3*/D0 + /D0*/D2*/D3 + D0*D1*/D2 + /D0*D1*D2 + D0*/D1*D2

That fixed the D segment.

I noticed an issue with the G segment.  This turned out to be a bug in their segment diagram.  If you look at the numbers 5 and 6, you’ll see that G is not listed.  Sigh.

While I was attempting to reverse engineer the formulas for this chip, I decided to add a simulation of this chip to my logic simulator.  I added code to allow me to read the .JED file in and set fuses according to the fuse map.  My intention was to verify that I had the right fuses set.  Of course, this turned into a different set of problems, all programming related, that I had to troubleshoot in order to make that work correctly.  The simulation software will pay dividends when I start to setup my next GAL circuit, because I can simulate the whole thing before I burn it to the chip and wire it to a circuit.

One lesson I learned is that it is very time consuming to type in the individual fuses.  It’s easier to build a set of formulas.  The number of formulas you can use is a maximum of 7 ORd terms for each output.  In other words, the D segment has 5 terms and they are setup for rows 26 through 29.  There is also a lamp test (LT).  So that’s a total of 6 terms.  One other input is the IC, which is connected to the enable lines for each OLMC.  What this means is that one row is not used and needs to be shut off.  So the PTD line for 31 should shut off that line (the fuse on line 31 actually belongs on line 30 to keep the pattern of fuses consistent).

The bottom line is that you have to get creative on your formulas.  Each segment can be lit for more than 7 different combinations of inputs, so it’s not possible to setup this circuit using terms of 4 like this:

/D = /D0*/D1*/D2*/D3 + /D0*D1*/D2*/D3 + etc.

Some combinations and minimization is required.  This also means that there are limits to what circuits the GAL16V8 can represent.

Here’s a picture of the actual circuit with a “2”, “A” and “F”:

Final Circuit

If you want a copy of the JEDEC file you can download it by clicking here.  You can download the logic simulator project by going to my GitHub account here.  Be aware that this software is still a work in progress.  So there will be changes in the near future.

Update

I was looking at this page:

I noticed that the “9” has the the “D” segment lit.  So the original logic formula in the book was correct.  However, that means that the segment list for “9” was wrong.  Here’s the correct segment list (for the diagram above):

 

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