The FPGA

I recently purchased an FPGA development board.  Specifically, the Mimas V2 Spartan 6 board.  There’s a really good introduction to this board which you can access by clicking here.  The board looks like this:

You can connect a micro-USB to USB cable to this board and program it from your PC.  Plus, the power from the USB can power the board for small circuits (there’s a power adapter that did not come with the board that you can use if the power requirements become too high).  I spent an evening going through the basic “hello world” circuit in the beginners guide and I was able to create a circuit that lit one of the small LEDs when pushing a button (I mentioned that this was the “hello world” circuit right?).  What motivated me to buy this board?

Programmable Logic – A Short History

Way back in the late 80’s (or 1978 according to Wiki) the PAL was invented.  This is a Programmable Array Logic device that is similar to the GALs that I used in my previous posts.  The basic chip came with an array of fuses that connected inputs to AND gates and you can blow fuses to “program” which input pins activated which AND gates.  Later, Generic Array Logic devices replaced these devices by substituting fuses with erasable links (electrically erasable floating gates).  These devices can be reprogrammed hundreds of times.  PALs and GALs can be used to replace several TTL logic chips for each programmable chip.

As chip sizes shrunk and more transistors could be fit on a chip new devices were invented.  CPLDs or Complex Programmable Logic Devices were nothing more than a dozen or more PALs on a chip with data buses that can be programmed to connect your sub-circuits (or modules).  The PAL-like structures on CPLDs are referred to as Macro Cells or Generic Logic Blocks.  Here’s an example of a logic block:

These blocks are wired together from a Global Routing Pool.  For the CPLD I used here, there are 16 GLBs connected with one large routing pool.

Along the same lines as the CPLD is the FPGA or Field Programmable Gate Array.  These devices are more complex than the CPLD and they are designed to be field programmable, usually incorporating flash memory.  According to Wiki, the earliest FPGAs were produced in the late 1970s.  FPGAs can contain logic blocks, memory blocks, shift registers, multiplexers and other circuits.  An entire system can be created on a single chip.  The Spartan 6 model XC6SLX9 model, used in the Mimas board I mentioned earlier, has 9,152 logic blocks and 576K of memory.  One of the largest Spartan FPGAs available today has 147,443 logic blocks and 4Meg of memory.

Using Verilog HDL

The circuitry inside an FPGA is too complex to be designed using fuse maps and schematics.  To make the job of creating a complex circuit easier, the Spartan FPGA is programmed using the Verilog Hardware Description Language (HDL).  The Verilog HDL language has “C”-like syntax and the Xilinx design tools editor is similar to Visual Studio.  This website has a pretty good tutorial on Verilog’s HDL language: ASIC World: Verilog.  I would highly recommend following the Numato Lab beginners guide to get used to the tools and the FPGA board.

The Mimas V2 Spartan-6 Board and Chip

When working on a circuit for the Mimas board this site is useful for looking up inputs and outputs: Mimas V2 Spartan 6 FPGA Development Board with DDR SDRAM.  All of the Spartan-6 chip specifications are located at the Xilinx site here: Xilinx Spartan-6 Documentation.  As I mentioned earlier the XC6SLX9 chip is used on the Mimas board.  The board schematics can be found here: Mimas V2 Schematics.

If you dig through the specifications for the Spartan FPGA, you’ll discover the CLB (Configurable Logic Block) organization which starts with this diagram:

As mentioned earlier, there are over 9000 of these blocks, of which, 4 are shown in the diagram above.  Each block contains a slice.  Each slice can be of three different circuit types: SLICEX, SLICEL and SLICEM.  Each with progressively more circuitry.  This table lists the features:

Here’s the diagram for the SLICEM:

You can refer to the documentation here to see the diagrams for the SLICEX and SLICEL.  In the SLICEM above, the 4 boxes on the left are the LUTs or Look Up Tables.  These can be used for combinatorial circuits on their own, or they can be programmed to connect any of the logic in the diagram into a complex subsystem.

Although the documentation lists the XC6SLX9 as having 9,152 logic cells, there are only 1,430 slices, which means that there are 715 CLBs.  The remaining logic cells must be circuitry other than the CLBs.  Further into the documentation is the diagram that shows how all the CLBs are connected together into an array:

Obviously, you would program modules that would be represented by a CLB and each module is interconnected together according to your defined inputs and outputs.  This simplifies the ability to design a large circuit by defining smaller sub-circuits, one module at a time.

So far, I’m only scratching the surface of what this device can do.  All I can think of is that this one chip can represent circuits beyond all the TTL chips I have stored in my box of parts (and I have quite the large collection of chips).   The price for the Mimas board is only $50 (I purchased it from here).  The Xilinx software used in the beginners guide is free, though you’ll have to fill out some information to download it (go here).

I’ll be following up with more posts on this subject as I learn what this board can do.

 

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