VHDL – Shift Register

My latest hobby is to learn VHDL and apply to the Mimas V2 FPGA board.  As with any language, reading about the language is all well and good, but attempting a real application is where the rubber hits the road.  I read through several tutorials and some introduction material to familiarize myself with some of the syntax.  I copied some code from example articles and observed how the code worked in simulation mode.  Then I finally decided to try and build a circuit without the code from a tutorial.  Keeping it somewhat simple, I chose to implement a shift register.  My goal was to create a 4-bit shift register that had one input that I could feed a “1” or a “0” per clock cycle.  I also wanted to see all 4 outputs to observe the data bits shifting down the line.  Here’s the circuit:

My first attempt was to just shift the outputs as though they are storage locations.  That caused an error: Cannot read from ‘out’ object output ; use ‘buffer’ or ‘inout’  I discovered that I needed some sort of storage inside my object (the flip-flops that represent my last state).  So I set up a “signal”:

signal dflipflops: STD_LOGIC_VECTOR(3 downto 0):="0000";

You can give your signal any name, I just called it dflipflops because that’s what popped into my head.  As you can see, the data in the signal can be pre-set to some value (in quotes because it’s a vector).

Next, I coded the reset.  I didn’t really need a reset for the simulation since I set the dflipflops to all zeros when the object is initialized.  However, if I decided to use this as a real circuit, I’d have to have a way to reset this at any time.  So I coded my reset as simple as possible:

if (reset = '1') then
    dflipflops <= "0000";
else
    -- shift logic goes here
end if;

Next, I hard-coded the logic of shifting bits (this is just the inner logic):

if (clock='1' and clock'event) then    
    dflipflops(3) <= dflipflops(2);
    dflipflops(2) <= dflipflops(1);
    dflipflops(1) <= dflipflops(0);
    dflipflops(0) <= datain;
end if;

I did this because I wanted to see if the simulation worked, and it didn’t.  I ended up with unknown outputs:

Yup, forgot to translate my signal back out to the outputs:

output(0) <= dflipflops(0);
output(1) <= dflipflops(1);
output(2) <= dflipflops(2);
output(3) <= dflipflops(3);

That worked:

Next, I converted to “for” loops and here’s the final code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- 4-bit shift register
entity shiftregister is port (
datain,clock,reset: in STD_LOGIC;
output: out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end shiftregister;

architecture Behavioral of shiftregister is
    
    signal dflipflops: STD_LOGIC_VECTOR(3 downto 0):="0000";
    
begin
    process (datain,clock,reset)
    begin
        if (reset = '1') then
            dflipflops <= "0000";
        else
            if (clock='1' and clock'event) then
                for i in 2 downto 0 loop
                    dflipflops(i+1) <= dflipflops(i);
                end loop;
                dflipflops(0) <= datain;
            end if;
        end if;
        
        for k in 3 downto 0 loop
            output(k) <= dflipflops(k);
        end loop;
        
    end process;
end Behavioral;

The test bench code is here:

ENTITY shiftregistertest IS
END shiftregistertest;
 
ARCHITECTURE behavior OF shiftregistertest IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT shiftregister
    PORT(
         datain : IN  std_logic;
         clock : IN  std_logic;
            reset : IN std_logic;
         output : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal datain : std_logic := '0';
   signal clock : std_logic := '0';
   signal reset : std_logic := '1';

     --Outputs
   signal output : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clock_period : time := 10 ns;
 
BEGIN
 
   -- Instantiate the Unit Under Test (UUT)
   uut: shiftregister PORT MAP (
          datain => datain,
          clock => clock,
             reset => reset,
          output => output
        );

   -- Clock process definitions
   clock_process :process
   begin
        clock <= '0';
        wait for clock_period/2;
        clock <= '1';
        wait for clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;    

      reset <= '0';
        
      wait for clock_period*6;

      -- test 1
      datain <= '1';
      wait for clock_period;
        
      datain <= '0';
      wait for clock_period*6;
      
      -- test 2
      datain <= '1';
      wait for clock_period*2;
                
      datain <= '0';
      wait for clock_period*6;

      wait;
   end process;

END;

For the test bench I first defaulted the reset to a “1” to force a reset at the beginning.  Then I set the reset back to “0” before testing data inputs.  The first test (test 1) feeds a “1” into the datain and then shifts it one clock cycle, then sets the datain back to “0”.  Then I shift 6 times to make the “1” shift all the way out of the shift register.  The next test (test 2), I set the datain to a “1” and shifted it in for two clock cycles, causing two “1”s to be inputted into the shift register.  Then I set datain back to “0” and shifted for 6 clock cycles to watch the two bits shift all the way through the shift register.  Here’s the simulation output:

The first test starts at 170ns and ends around 210ns.  The second test starts at 240ns and ends at 290ns.

One thing I noticed about the editor is that you must select the test source file before double-clicking on “Simulate Behavioral Model”:

Otherwise, you’ll get a result like this:

You also need to close the ISim window before you can run another simulation otherwise, you’ll get an error like:

ERROR:Simulator:904 – Unable to remove previous simulation file isim/shiftregistertest_isim_beh.exe.sim/shiftregistertest_isim_beh.exe. Please check if you have another instance of this simulation running on your system, terminate it and then recompile your design. System Error Message: boost::filesystem::remove: Access is denied: “isim\shiftregistertest_isim_beh.exe.sim\shiftregistertest_isim_beh.exe”ERROR:Simulator:861 – Failed to link the design

Once this error occurs, you’ll need to close the ISim window, then you will need to right-click on the “Simluate Behavioral Model” and select “rerun all”.  Double-clicking just gives this error:

INFO:ProjectMgmt – The selected process was not run because a prior process failed.

One other thing I find annoying about the editor is that there is no file name change capability.  I’ve attempted to change the name of a file and ended up with a mess.  There is a lot of smart linking that goes on between the project and the files that belong to it.  My quick fix is to create a new file with the new name and scrape the code from the old source and paste into the new source.  Then I delete the old file.  It’s dumb and dirty, but it’s also pretty quick.

Other than the few quirks that I’ve worked around, I am happy that the editor is similar to Visual Studio in commands and syntax highlighting.

 

FPGA – Hex LED Display

After finishing the beginner’s guide for the Mimas V2 Development Board, I decided to try my hand at a circuit that I previously built with the GAL16V8 chip.  I already had the PDS file for the BCD to Hexadecimal LED display, so I decided to try that.  First, I needed to figure out what I could use for inputs.  The Mimas board has an 8-position DIP switch.  I used switch 1 through 4 for the BCD input.  I also used push button switch number 1 for the lamp test input.  If you go to this website, you can find all the schematics that show inputs and outputs.  Here are the inputs:

According to the diagram above, I chose to use M18 for the lamp test and dip switches F17, F18, E16, E18 for my BCD inputs.  All switches are active low, so I needed pull-up resistors and had to reverse the input logic to the module (a zero is inputted when the switch is ON).

Next, the outputs.  There are three 7-segment displays, so I chose display 1.  To enable the display, I applied a zero to the enable transistor.  Also, I had to disable the other two displays by applying a “1”.  Here’s the schematic:

So B3 must be set to “0” and A2 and B2 must be set to a “1”.  Then segment A is A3, segment B is B4, segment C is A4, etc.  The UCF file for the program will look like this:

# User Constraint File for BCD to 7-Segment Hex Display implementation on Mimas V2

NET "A" LOC = A3;
NET "B" LOC = B4;
NET "C" LOC = A4;
NET "D" LOC = C4;
NET "E" LOC = C5;
NET "F" LOC = D6;
NET "G" LOC = C6;
NET "EN1" LOC = B3;
NET "EN2" LOC = A2;
NET "EN3" LOC = B2;

# Switches.
# Internal pull-ups need to be enabled since 
# there is no pull-up resistor available on board
NET "D0" PULLUP;
NET "D1" PULLUP;
NET "D2" PULLUP;
NET "D3" PULLUP;
NET "LT" PULLUP;

NET "D0" LOC = F17;
NET "D1" LOC = F18;
NET "D2" LOC = E16;
NET "D3" LOC = E18;
NET "LT" LOC = M18;

Now, it’s time to create the logic.  I discovered the AND, OR, NOR, etc. circuits from this tutorial: Verilog Tutorial.  So I created OR/AND combinations for each segment like this:

and (a1, D0, D2);
and (a2, D0, !D3);
and (a3, !D1, !D2);
and (a4, !D1, D2, D3);
and (a5, !D0, !D2, D3);
and (a6, D1, D2, !D3);
nor (A, a1, a2, a3, a4, a5, a6, !LT);

This came from the following formula used in my GAL16V8 circuit:

/A = /RBO*/D0*/D2 + /RBO*/D0*D3 + /RBO*D1*D2 + /RBO*D1*/D2*/D3 + /RBO*D0*D2*/D3 + /RBO*/D1*/D2*D3 + LT

I did not implement the RBO (Ripple Blanking Output).  So, I removed all the /RBO terms.  Then I flipped all the “NOT” to be positive and all the positive to be “NOT”.  Instead of !D0 AND !D2, the first term is D0 AND D2.  Last, I ORd the lamp test (LT) with the results.  The LT button is also inverted because pressing the button produces a zero.  So you’ll notice that there is a !LT in each OR term. Since the segments are active low, I had to change all of my OR’s to NOR (the display looked rather interesting with the segments inverted).

The last part of the logic was forcing which display was on:

assign EN1 = 0; // enable digit 1
assign EN2 = 1; // disable digit 2
assign EN3 = 1; // disable digit 3

I wasn’t sure how large each Spartan 6 logic block was, so I just typed this in and expected the program to give me an error if I exceeded the number of AND/OR gates available.  Apparently, I didn’t reach that limit.  The program console shows that my program used 4 LUTs out of 5,720:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          4 out of   5,720    1%
    Number used as logic:                        4 out of   5,720    1%
      Number using O6 output only:               1
      Number using O5 output only:               0
      Number using O5 and O6:                    3
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   1,440    0%

Apparently, the LUT (Look Up Table) is used to represent combinatorial circuits.  There is a description of the LUT in this document: Spartan-6 FPGA Configurable Logic Block User Guide

The function generators in Spartan-6 FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs – A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement any arbitrarily defined six-input Boolean function.
Basically, the LUT is a logic table representation of my discrete boolean logic.  Technically, I could have provided a lookup table definition, similar to mapping out a circuit in Read Only Memory.
The Code
Here’s the full listing of the UCF file:
# User Constraint File for BCD to 7-Segment Hex Display implementation on Mimas V2

NET "A" LOC = A3;
NET "B" LOC = B4;
NET "C" LOC = A4;
NET "D" LOC = C4;
NET "E" LOC = C5;
NET "F" LOC = D6;
NET "G" LOC = C6;
NET "EN1" LOC = B3;
NET "EN2" LOC = A2;
NET "EN3" LOC = B2;

# Switches.
# Internal pull-ups need to be enabled since 
# there is no pull-up resistor available on board
NET "D0" PULLUP;
NET "D1" PULLUP;
NET "D2" PULLUP;
NET "D3" PULLUP;
NET "LT" PULLUP;

NET "D0" LOC = F17;
NET "D1" LOC = F18;
NET "D2" LOC = E16;
NET "D3" LOC = E18;
NET "LT" LOC = M18;
And the V file:
module HexLED(D0,D1,D2,D3,LT, A, B, C, D, E, F, G, EN1, EN2, EN3);
    input wire D0;
    input wire D1;
    input wire D2;
    input wire D3;
    input wire LT;
    
    output wire A;
    output wire B;
    output wire C;
    output wire D;
    output wire E;
    output wire F;
    output wire G;
    output wire EN1;
    output wire EN2;
    output wire EN3;
    
    // /D0*/D2 + /D0*D3 + D1*D2 + D1*/D2*/D3 + D0*D2*/D3 + /D1*/D2*D3
    and (a1, D0, D2);
    and (a2, D0, !D3);
    and (a3, !D1, !D2);
    and (a4, !D1, D2, D3);
    and (a5, !D0, !D2, D3);
    and (a6, D1, D2, !D3);
    nor (A, a1, a2, a3, a4, a5, a6, !LT);
    
    // /D2*/D3 + /D0*/D2 + /D0*/D1*/D3 + D0*D1*/D3 + D0*/D1*D3
    and (b1, D2, D3);
    and (b2, D0, D2);
    and (b3, D0, D1, D3);
    and (b4, !D0, !D1, D3);
    and (b5, !D0, D1, !D3);
    nor (B, b1, b2, b3, b4, b5, !LT);
    
    // D0*/D1 + D0*/D2 + /D1*/D2 + D2*/D3 + /D2*D3
    and (c1, !D0, D1);
    and (c2, !D0, D2);
    and (c3, D1, D2);
    and (c4, !D2, D3);
    and (c5, D2, !D3);
    nor (C, c1, c2, c3, c4, c5, !LT);
    
    // /D0*/D1*D3 + /D0*/D2*/D3 + D0*D1*/D2 + /D0*D1*D2 + D0*/D1*D2
    and (d1, D0, D1, !D3);
    and (d2, D0, D2, D3);
    and (d3, !D0, !D1, D2);
    and (d4, D0, !D1, !D2);
    and (d5, !D0, D1, !D2);
    nor (D, d1, d2, d3, d4, d5, !LT);
    
    // /D0*/D2 + D2*D3 + /D0*D1 + D1*D3
    and (e1, D0, D2);
    and (e2, !D2, !D3);
    and (e3, D0, !D1);
    and (e4, !D1, !D3);
    nor (E, e1, e2, e3, e4, !LT);
    
    // /D0*/D1 + /D2*D3 + D1*D3 + /D0*D2 + /D1*D2*/D3
    and (f1, D0, D1);
    and (f2, D2, !D3);
    and (f3, !D1, !D3);
    and (f4, D0, !D2);
    and (f5, D1, !D2, D3);
    nor (F, f1, f2, f3, f4, f5, !LT);
    
    // D1*/D2 + D0*D3 + /D2*D3 + /D0*D1 + /D1*D2*/D3
    and (g1, !D1, D2);
    and (g2, !D0, !D3);
    and (g3, D2, !D3);
    and (g4, D0, !D1);
    and (g5, D1, !D2, D3);
    nor (G, g1, g2, g3, g4, g5, !LT);
    
    assign EN1 = 0; // enable digit 1
    assign EN2 = 1; // disable digit 2
    assign EN3 = 1; // disable digit 3
    
endmodule
 

The FPGA

I recently purchased an FPGA development board.  Specifically, the Mimas V2 Spartan 6 board.  There’s a really good introduction to this board which you can access by clicking here.  The board looks like this:

You can connect a micro-USB to USB cable to this board and program it from your PC.  Plus, the power from the USB can power the board for small circuits (there’s a power adapter that did not come with the board that you can use if the power requirements become too high).  I spent an evening going through the basic “hello world” circuit in the beginners guide and I was able to create a circuit that lit one of the small LEDs when pushing a button (I mentioned that this was the “hello world” circuit right?).  What motivated me to buy this board?

Programmable Logic – A Short History

Way back in the late 80’s (or 1978 according to Wiki) the PAL was invented.  This is a Programmable Array Logic device that is similar to the GALs that I used in my previous posts.  The basic chip came with an array of fuses that connected inputs to AND gates and you can blow fuses to “program” which input pins activated which AND gates.  Later, Generic Array Logic devices replaced these devices by substituting fuses with erasable links (electrically erasable floating gates).  These devices can be reprogrammed hundreds of times.  PALs and GALs can be used to replace several TTL logic chips for each programmable chip.

As chip sizes shrunk and more transistors could be fit on a chip new devices were invented.  CPLDs or Complex Programmable Logic Devices were nothing more than a dozen or more PALs on a chip with data buses that can be programmed to connect your sub-circuits (or modules).  The PAL-like structures on CPLDs are referred to as Macro Cells or Generic Logic Blocks.  Here’s an example of a logic block:

These blocks are wired together from a Global Routing Pool.  For the CPLD I used here, there are 16 GLBs connected with one large routing pool.

Along the same lines as the CPLD is the FPGA or Field Programmable Gate Array.  These devices are more complex than the CPLD and they are designed to be field programmable, usually incorporating flash memory.  According to Wiki, the earliest FPGAs were produced in the late 1970s.  FPGAs can contain logic blocks, memory blocks, shift registers, multiplexers and other circuits.  An entire system can be created on a single chip.  The Spartan 6 model XC6SLX9 model, used in the Mimas board I mentioned earlier, has 9,152 logic blocks and 576K of memory.  One of the largest Spartan FPGAs available today has 147,443 logic blocks and 4Meg of memory.

Using Verilog HDL

The circuitry inside an FPGA is too complex to be designed using fuse maps and schematics.  To make the job of creating a complex circuit easier, the Spartan FPGA is programmed using the Verilog Hardware Description Language (HDL).  The Verilog HDL language has “C”-like syntax and the Xilinx design tools editor is similar to Visual Studio.  This website has a pretty good tutorial on Verilog’s HDL language: ASIC World: Verilog.  I would highly recommend following the Numato Lab beginners guide to get used to the tools and the FPGA board.

The Mimas V2 Spartan-6 Board and Chip

When working on a circuit for the Mimas board this site is useful for looking up inputs and outputs: Mimas V2 Spartan 6 FPGA Development Board with DDR SDRAM.  All of the Spartan-6 chip specifications are located at the Xilinx site here: Xilinx Spartan-6 Documentation.  As I mentioned earlier the XC6SLX9 chip is used on the Mimas board.  The board schematics can be found here: Mimas V2 Schematics.

If you dig through the specifications for the Spartan FPGA, you’ll discover the CLB (Configurable Logic Block) organization which starts with this diagram:

As mentioned earlier, there are over 9000 of these blocks, of which, 4 are shown in the diagram above.  Each block contains a slice.  Each slice can be of three different circuit types: SLICEX, SLICEL and SLICEM.  Each with progressively more circuitry.  This table lists the features:

Here’s the diagram for the SLICEM:

You can refer to the documentation here to see the diagrams for the SLICEX and SLICEL.  In the SLICEM above, the 4 boxes on the left are the LUTs or Look Up Tables.  These can be used for combinatorial circuits on their own, or they can be programmed to connect any of the logic in the diagram into a complex subsystem.

Although the documentation lists the XC6SLX9 as having 9,152 logic cells, there are only 1,430 slices, which means that there are 715 CLBs.  The remaining logic cells must be circuitry other than the CLBs.  Further into the documentation is the diagram that shows how all the CLBs are connected together into an array:

Obviously, you would program modules that would be represented by a CLB and each module is interconnected together according to your defined inputs and outputs.  This simplifies the ability to design a large circuit by defining smaller sub-circuits, one module at a time.

So far, I’m only scratching the surface of what this device can do.  All I can think of is that this one chip can represent circuits beyond all the TTL chips I have stored in my box of parts (and I have quite the large collection of chips).   The price for the Mimas board is only $50 (I purchased it from here).  The Xilinx software used in the beginners guide is free, though you’ll have to fill out some information to download it (go here).

I’ll be following up with more posts on this subject as I learn what this board can do.

 

Programming the GAL22V10

In previous blog posts I showed how the GAL16V8 operated and how to program it (see here and here).  In this blog post I’m going to discuss the differences between the 16V8 and the 22V10. Here’s the specification sheet for the GAL22V10: Lattice GAL22V10 Specifications.

On first inspection, both devices look identical, except for the increased number of inputs and outputs.  The specifications are straightforward once you know what to expect.  If you’re familiar with the 16V8 and have never used the 22V10, there are some confusing differences.

Here’s the full fuse map for the GAL22V10:

0 - 5807 matrix

5808 S0 for OLMC 0 (active low/high)
5809 S1 for OLMC 0 (registered/combinatorial)

5810 S0 for OLMC 1
5811 S1 for OLMC 1

5812 S0 for OLMC 2
5813 S1 for OLMC 2

5814 S0 for OLMC 3
5815 S1 for OLMC 3

5816 S0 for OLMC 4
5817 S1 for OLMC 4

5818 S0 for OLMC 5
5819 S1 for OLMC 5

5820 S0 for OLMC 6
5821 S1 for OLMC 6

5822 S0 for OLMC 7
5823 S1 for OLMC 7

5824 S0 for OLMC 8
5825 S1 for OLMC 8

5826 S0 for OLMC 9
5827 S1 for OLMC 9

5828 - 5891 Signature

No PTD Fuses

You’ll notice that there are no PTD (Product Term Disable) fuses.  This device doesn’t have any.

No Common Mode Bits

Next, the mode bits are missing (the GAL16V8 had 3 modes controlled by fuses 2192 and 2193).  The OLMC modes for the GAL22V10 are built into the S0 and S1 bits.  There are only two modes: Registered and Combinatorial, controlled by the S1 bit.  Each OLMC can be programmed separately, which means that you can designate which OLMCs are Registered and which are Combinatorial.  The S0 bit controls active high and active low outputs for each OLMC.

Variable Rows per OLMC

The next complication to this device is that the matrix of fuses that control the AND gates is variable in the number of rows.  The GAL16V8 had a simple arrangement of 8 rows for each OLMC.  In the 22V10, there are a variable number of rows for each OLMC starting with 8, then incrementing by 2 for each OLMC until 16 and then decrementing by 2 until the last OLMC has 8 inputs.  You can see the number of inputs for each OLMC in the functional block diagram:

If you have an equation with 13 terms like this arbitrary example:

OUT = A*B + C + /B + A*/C + D*E + C*D + A*D*E + A*/B*D + B*/D + /B*C*E + C*E*F + E*/F + /E*C*D

You’ll need to make sure it lines up with an OLMC that has more than 12 rows.  This equation will not fit on OLMC 0, 1, 2 or OMLC 7, 8 or 9.  What this means is that you will have to rearrange your output pins for circuits that use more than 8 rows because each OLMC is tied to a specific output pin.

The number of Fuses Per Row is 44

Also, since there are more inputs, then there are also more columns in the matrix.  The number of columns is 44, which is not a round binary number.  The number of columns is determined by the total number of inputs and feedback wires.  Each input and feedback takes 2 columns (the signal and the inverse of the signal.

Preset and Reset Lines

Two extra lines can be used to control reset and set for all registers (assuming you use the registered mode).  The reset line causes the starting fuse of the first OLMC to be 44 instead of zero.  The purpose of the reset line is to reset all the registers used in the device.  You can connect any logic to the reset line to perform reset via a pin, or some combination of logic.  The same goes for the preset line, which is the line that is positioned after the last matrix row starting at fuse 5764 (row 131).

Other Differences

The clock pin is still pin 1 as in the GAL16V8.  The difference is that in the GAL16V8, the clock pin is not used at all in modes that don’t use the registers.  So pin 1 feeds fuse columns 2 and 3.  In the GAL22V10, the clock can control zero or more registered outputs because registered outputs can be selected per OLMC.  Therefore the clock pin is wired to fuse columns 0 and 1 and to the register clock inputs.

The active high/low logic is performed on the output of the D-flip/flop of the GAL22V10, where it is on the input of the GAL16V8 (controlled by an XOR gate).

Using PALASM for DOS

PALASM4 for DOS is still around.  You can to this website and scroll to the bottom to download the RAR file: S100 Computers.  This article is rather old, but it still works.  Here’s the steps I took to get this working:

  1. Make sure you have DOSBOX installed.
  2. Download the RAR file from the article above.
  3. You can use 7-zip to unzip the RAR file.  Right-click on the RAR file and use extract files.  That will maintain the directory structure.  I used d:\palasm.
  4. Start DOSBOX.
  5. Type: “MOUNT c d:\palasm
  6. Type: C:
  7. Type: SET PALASM=c:\
  8. Type: PALASM

Now you should see this screen (after the intro screen):

Select “Retrieve existing design” and type in your filename (I’m assuming you created a file, or you can copy one of the .pds files in the EXAMPLES directory.  Hit the F10 button, then use the right-arrow to select the RUN menu and hit enter (Compilation is the first choice).  Then just hit F10 to compile your PDS file.  You’ll see some processing and then it should end with no errors or warnings:

You can hit ESC to return control to the menus.  Switch back to your directory in windows and you can see that an XPT and JED file were created.  Open your JED file to see the fuse map results:

Finally…

PALs and GALs are obsolete and the digital world has moved onto FPGAs.  These devices are still available and are still useful for hobby purposes.  They can be purchased through Jameco or DigiKey.  PALASM is also obsolete, hence the reason that it only exists in FORTRAN and DOS versions.  If you’re still using these devices, leave me a comment or hit the like button.

 

Building an ALU From EPROM – The Circuit

When I wrote my blog post about building an ALU from an EPROM, I intended to use an EPROM from my old bag of parts.  Unfortunately, none of my old UV erasable PROMs worked with the programmer.  I’m assuming they are old and not usable.  So I purchased a pair of 28C64’s from Jameco Electronics.  These are Electrically Erasable PROMs, so I don’t need to drag out my UV light and wait 30 minutes (or so) for them to erase before reprogramming them.

After I programmed the EEPROM, I had to make a diagram of the pins.  The pin out for the memory chip is organized by address lines and data lines and I’m pretending that the address lines are inputs and the data lines are just outputs (technically they are bi-directional).  Here’s a diagram of what I ended up with:

Technically, I can re-arrage the pins by reprogramming the data and pretending that pins 21, 23-25 are carry in and the function selectors.  Then all the A0-A3 and B0-B3 could be arranged on the left side of the chip.  It really only matters if you are concerned about circuit board layout.  At the moment, I just want to show that it can be done.

Next, I decided to use my 7-segment hex display driver with a 7-segment display to show the output from F0-F3.  This took a bit of extra wiring, but it’s easier to read than 4 LED lights.  Here’s the chip pinout using the GAL16V8 from this blog post (click here):

All that is needed is a breadboard, resistors, a 7-segment display and a bunch of wires.  This is my quick-and-dirty circuit:

For this circuit, I set S0-S2 to the ADD mode (S0=H, S1=H, S2=L).  The small chip in the lower right is the GAL that I programmed in an earlier article.  I also set the carry in as H (represents zero) and set A0 and B0 to H, with all other An and Bn to L.  As you can see 1 + 1 = 2.

One of the reasons I’m demonstrating this idea of using a ROM to represent a circuit is that a simple logical circuit can be temporarily represented as a memory chip.  Then a real circuit can be designed to be substituted.  I have not tested all possible inputs and outputs of this circuit and, more importantly, I have not tested the limits of the speed that this circuit would operate it.  I already know that the answer to my speed question is going to be “disappointingly slow”.

Purpose

Knowing that this will be a slow circuit, what’s the purpose?  The first purpose would be to create a prototype of a circuit that you plan to build.  If you’re building a machine that will require some programming, then it might be best to create a slow version of the machine so another programmer can create and test the software before the machine is complete.

This type of circuit design can also be used for educational purposes.  You can prepare EEPROMs with the circuits you’ll need for class instruction to support your lecture.  The EEPROM represents a black box of the circuit that your class can use without actually building a complete circuit.  In this instance an ALU.  The circuit could then be reprogrammed for a different purpose in a future lecture.

 

Generic Array Logic Hexadecimal Display

I’ve always wanted a decoder that did more than the TTL 7447 BCD to seven segment display decoder did.  I wanted the full hexadecimal output.  One of my first real projects for the GAL was to create such a chip.  I have an old PAL databook that was published by National Semiconductor in 1982.  I pulled the book off my shelf, just to see what information was in it and to my surprise was a hex display “Application suggestion”.  What luck!  Here’s a picture of the page in the book (click for larger image):

What I didn’t realize when I started this project was that it was going to be a real learning experience.  At first, the chip did not produce any outputs at all.  Then I had issues with several of the segments lighting all the time.  Typing the data into the JEDEC file was tedious and verifying that the fuses were correct was more tedious.  The first problems I found were due to my translation to the .JED file.  I expected that to occur, so I went over the file several times in detail.  Once I determined that I typed it in as it was shown in the book, I began to suspect that the book was wrong (that turned out to be an understatement).

I found a few typos in the diagram above.  First, the PTD fuses were not all correct.  There’s a pattern that they followed when the fuses were set and I noticed that some of the PTD fuses (the “X”s on the AND gates to the right side of the diagram) were not “X”d when the row was empty.  I fixed those and obtained some results.

In order to fix the segment problems I took a look at these two pages:

The page on top is the design page with PALASM logic formulas.  The bottom page is the segment diagram showing which segments will light up given a set of inputs D0-D3.  Both diagrams have mistakes.  I printed a bunch of segment display diagrams so I could work out the logic formulas and determine which formula would cause each segment to light up.  That appeared to be the way the fuses were laid out in the chip.  I focused on the D segment first:

The logic formula for the D segment was listed as follows (ignoring the RBO and LT lines):

/D = /D1*D3 + /D0*/D2*/D3 + D0*D1*/D2 + /D0*D1*D2 + D0*/D1*D2

What this translates to is that the D output (inverted) will be equal to the not D1 AND D3, or the not D0 AND not D2 AND not D3, etc.  As you can tell by my hand writing the /D1*D3 causes all the D segments to light for the binary combinations where D1 is zero and D3 is a one.  I wrote a 25 next to each of those because this logic is used on line 25 of the fuse map.  Unfortunately, this combination occurs for 1001, which should be segments ABCFG (no D segment).  To fix this, I added a /D0 to the equation:

/D = /D1*D3*/D0 + /D0*/D2*/D3 + D0*D1*/D2 + /D0*D1*D2 + D0*/D1*D2

That fixed the D segment.

I noticed an issue with the G segment.  This turned out to be a bug in their segment diagram.  If you look at the numbers 5 and 6, you’ll see that G is not listed.  Sigh.

While I was attempting to reverse engineer the formulas for this chip, I decided to add a simulation of this chip to my logic simulator.  I added code to allow me to read the .JED file in and set fuses according to the fuse map.  My intention was to verify that I had the right fuses set.  Of course, this turned into a different set of problems, all programming related, that I had to troubleshoot in order to make that work correctly.  The simulation software will pay dividends when I start to setup my next GAL circuit, because I can simulate the whole thing before I burn it to the chip and wire it to a circuit.

One lesson I learned is that it is very time consuming to type in the individual fuses.  It’s easier to build a set of formulas.  The number of formulas you can use is a maximum of 7 ORd terms for each output.  In other words, the D segment has 5 terms and they are setup for rows 26 through 29.  There is also a lamp test (LT).  So that’s a total of 6 terms.  One other input is the IC, which is connected to the enable lines for each OLMC.  What this means is that one row is not used and needs to be shut off.  So the PTD line for 31 should shut off that line (the fuse on line 31 actually belongs on line 30 to keep the pattern of fuses consistent).

The bottom line is that you have to get creative on your formulas.  Each segment can be lit for more than 7 different combinations of inputs, so it’s not possible to setup this circuit using terms of 4 like this:

/D = /D0*/D1*/D2*/D3 + /D0*D1*/D2*/D3 + etc.

Some combinations and minimization is required.  This also means that there are limits to what circuits the GAL16V8 can represent.

Here’s a picture of the actual circuit with a “2”, “A” and “F”:

Final Circuit

If you want a copy of the JEDEC file you can download it by clicking here.  You can download the logic simulator project by going to my GitHub account here.  Be aware that this software is still a work in progress.  So there will be changes in the near future.

Update

I was looking at this page:

I noticed that the “9” has the the “D” segment lit.  So the original logic formula in the book was correct.  However, that means that the segment list for “9” was wrong.  Here’s the correct segment list (for the diagram above):

 

Digital Electronics for the Beginner (Part 2)

I’m going to continue this series while it’s still fresh in my mind.  In case you missed it, part 1 is here.

I learned electronics when I was in High School.  I had two years of electronics classes and I also built circuits out of digital logic gates as a hobby.  This is in the late 70’s when Radio Shack sold chips in packages on the rack.  One of the problems with the subject of electronics is that most of the knowledge you need to become an “expert” is very dry.  To compound the problem, the subject is always taught with the basics of DC circuits and then the subject works up to AC circuits.  All rather dry stuff until you arrive at the transistor.  Then the subject of oscillators and amplifiers will put one to sleep just as fast (unless you’re interested that subject).  If you know nothing about electronics you should still be able to buy the parts I listed in my last blog post and assemble the circuits I described without too much trouble.

In my last blog post I also assumed you have some small hand tools.  If you purchased everything on the list provided, you might be wondering how to strip the ends of the wire or cut the wire to length.  That would require a pair of diagonal cutters and maybe a pair of wire strippers.  You might also need a pair of needle nose pliers to hold short wires.  You can use scissors to cut 22 gauge wire, but your scissors might not be good for paper after that.  The only tool you really need is this wire cutter/stripper:

You can find them at Jameco and they are cheaper here.

Larger Circuits

If you built the circuits in the previous blog post, you’ll realize that each circuit only involved one gate.  Larger circuits can be built by connecting outputs of one gate to inputs of other gates.  If you bought all the chips on the list that I provided, you should have 12 Inverters and an assortment of 40 other gates.  You can create quite a large circuit with that many chips.

There are several problems you’ll run into if you keep building larger and larger circuits.  First, you’ll probably run out of breadboard space.  That’s easy to fix, just buy a bigger breadboard or a second board.  But that’s not what I’m getting at here.  Circuits have limitations as well.  You should be aware of the limitations that you might run into and how to solve them.

One limitation is your power supply.  If you wire up enough LEDs and chips, you can exceed the total amperage of your power supply.  When that occurs, then your power supply will not be able to maintain the voltage that you have set and it might trip the built-in power protection.  If this happens, you’ll need to get a larger power supply to run your circuit.

If your circuit is complicated and you connect a lot of gates together, you could run into the fan-out limitation.  Each output can only drive so much current.  This rating is listed in the spec sheet and you need to compute the current rating of each input your connected to in order to see if the output can handle it.  This should only be looked at if you are connecting to more than about maybe 6 or 8 gates, or if you measure the output of your gate and it can’t achieve the voltage necessary to trigger a high (or maybe a low).  You’ll need a meter to measure the voltage.  This will probably be your first test tool.  Don’t splurge for the expensive meter, just buy something like this:

Jameco sells this meter for $6.95.  Click here.  You can also shop around, Amazon might have an even better price.

Eventually, you’ll get into clocking circuits.  You can build some pretty fast circuits that can do sequences, computations and other crazy stuff.  When you get to this level of sophistication you’ll need to understand the basics of DC and AC circuits.  Why?  Because the real-world is not perfect.  A signal traveling down a wire and through a circuit takes physical time.  It’s lightning fast, but the delay is still there.  Voltages will not switch exactly between 0 volts and 5 volts.  There is a transition time and there are overshoots (when the signal spikes beyond the top of the square wave).  This overshoot looks like this:

real-square-waveAs you increase the speed of your circuit, this imperfection becomes a real problem.

Circuit switching can cause spikes to form on your power.  This can transmit to adjacent chips and cause errors in your circuit.  There is a simple remedy for that and it involves installing a capacitor near the power lead of your chips.  If you own an oscilloscope, you can put your probe on the power supply and see the spikes.  Here’s a photo that shows how capacitors (orange and yellow) are installed near memory chips on an old circuit board:

old_memory_boardNone of these “problems” are difficult to overcome.  You just need to be aware that they exist.  Oh, and there are so many more complicated issues that can occur.  Don’t let that scare you away from enjoying this hobby/career.

The Binary System

The binary system only has two symbols a zero and a one.  So numbers in binary take more digits than the decimal system that people are most familiar with.  Here’s an example of a 3-digit binary number counting from zero to 7 (binary is on the left and decimal is on the right):

When we add two numbers together in binary, it’s similar to decimal.  If both inputs are zero, then the output is zero.  If either input is a one, then the output is a one.  If both inputs are one, then we need to set the output to zero and carry the one.  This is just like carrying a one when we add 9+1 in the decimal system:

Your Next Circuit

Let’s build a binary adder.  We’re going to start out with the simplest circuit.  The one-bit half adder.  Here’s the circuit and truth table:

 

The first thing you’ll notice is the exclusive or gate.  You can purchase a TTL XOR gate (74LS86) or you can build one out of NAND gates.  Which is what we’re going to do.  So change your circuit to this:

The NAND gate and the NOR gate have a special relationship to digital circuits.  They are the universal gates.  Any gate types can be built with just NAND gates (or just NOR gates).  Here is a list of gates and their NAND gate substitution:

Now, if you run out of OR gates, you can build one out of any spare NAND gates.

Back to our fancy half-adder circuit.  I’m going to add the pin numbers to the NAND gate chip so you can wire this easily:

Setup your breadboard and find a 74LS00 and a 74LS08.  Plug these into your breadboard like this:

I added two LEDs with resistors (100 ohm) connecting the cathode to ground.  This is the same as in previous circuits.  You can pre-check your LED wiring by connecting the other side to positive and see if the LED lights up.  If it does, then you’re good.  If it doesn’t light up, then reverse the LED leads and try again. Also, make sure the markings on your chips face up (look for pin 1).

Wire the output of the sum (NAND gate pin 11) to the lower LED and wire the output of the carry (AND gate pin 3) to the upper LED:

If you have power applied, you’ll notice that the carry LED has lit up.  That’s because there is nothing connected to the inputs of your AND gates and if you remember, TTL treats an unconnected input as a “1” or high.  Now wire up the rest of your gates.  I’ve taken photos of all 4 combinations of inputs, from left to right, 00, 01, 10, 11 (click to zoom):

Here’s another copy of the truth table to check your work:

Review

So what did we learn?

  • The NAND and NOR gates are universal and can replace any other gate.
  • The binary system only uses the numbers zero and one.
  • Using a simple circuit we can add two one-bit numbers together.
 

Generic Array Logic Devices

I’ve been blogging a bit about digital electronics lately.  One of the devices that I have never had the opportunity to experiment with is the Programmable Array Logic or PAL.  The last time I built a circuit was when I was in College in the early 90’s.  At that time I owned a Mac Plus and a 386sx generic PC.  With my limited resources (see college student), I couldn’t afford a device to program PALs or EPROMs.  I ended up building my own EPROM programmer to program some 2716s and 2732s.  Those days are long gone.  Now things are cheaper and better.  Now the PAL has been kicked to the curb and even the GAL is obsolete.  Fortunately, the GAL was manufactured for so long that there are a lot of cheap chips available.  I’m going to get into the weeds on the GAL16V8 device.  My purpose is to publish some information that is very difficult to find on the web.  Lattice is the company that made these devices and they have stopped manufacturing them as of 2014 (not to worry, there are substitutes from other companies).

Programming the GAL16V8 Device

I own the MiniPro programmer which can program a bazillion different devices.  I bought it to program EPROMs, but it’ll do PALs, GALs and a bunch of other embedded devices.  It’s a simple USB connected device and it’s cheap.  Here’s the product website: TL866 Universal Programmer.  I wasn’t able to find a copy of the PALASM program in any language other than FORTRAN and I decided I needed to make progress on programming this chip, so I reverse engineered the JEDEC file and manually set the fuse links.  Technically, the GAL doesn’t have any fuses.  The old PALs used to have a fuse link on each grid wire and you blew out all the fuses for pathways you didn’t want.  This leaves the paths you want intact which form a circuit.  Your programmer blows the fuses based on a JEDEC file.  If you make a mistake and blow a fuse you didn’t intend to blow, well, you throw away the chip and program another one.  The fuses are permanent, like a PROM (Programmable Read Only Memory).  The GAL uses flash memory to represent the fuses and they can be erased and reprogrammed.  This is very convenient because it took me about 20 tries to get my first GAL to do something simple.

The JEDEC file is a text file that contains the fuse definitions.  I discovered the details of this file by opening my programmer window and saving a blank file (after selecting the correct device).  The programmer created a .JED file and I opened it with Sublime to see what format it was in.  I was pleasantly surprised that it was in text format and not binary.  So I changed some of the “1”s into “0”s, saved the file and read it back into my programmer software and it worked.  Next was the task of figuring out the layout.  This took a lot of research (a.k.a. Internet searches) plus trial and error.

First, let’s describe the device.

How the GAL16V8 Works

The spec for the device can be found here: GAL16V8.  If you scroll down to page 8 you’ll see this diagram (this is just the top):

This diagram shows the grid of wires that connect the internals.  The OLMC is a configurable block of logic that can determine how the chip behaves.  Each row of wires can connect to any wire in the 32 columns of wires.  However, each row is not really one wire.  Each row represents the AND of each wire leading to the OLMC.  You can see the tiny AND gates to the left of the OLMC blocks:

Inside the OLMC is an OR gate that ORs all the ANDed lines together.  Like this:

What this really represents is something like this:

The idea is to set fuses to connect input lines to the inputs of the AND gates.  Pin 1 and Pin 2 inputs can be setup so that one of the AND gates will trigger an output if both inputs are a “1”.  Here’s an example of the fuses to set (all others will be removed):

The left “X” represents a connection from pin 2 high and the right “X” represents the connection from pin 1 high (pin 1 wraps around the OLMC).

You might have noticed the little “PTD” and “2128” at the top of the GAL diagram.  That fuse allows you to turn off any AND gate that you don’t want to include in your circuit (PTD stands for Product Term Disable).  So you need to keep fuse 2129, but you can remove fuses for 2128 and 2130 through 2135.  This will prevent any other lines from interfering with your first circuit.

Next, you’ll need to understand that all the OLMCs can be programmed to behave in different ways.  To get them to behave as a simple OR gated output, you can set the SYN and AC0 fuses to 1 and 0 respectively.  SYN is fuse number 2192 and AC0 is fuse number 2193 (the last two fuses in the file).  For the first OLMC you’ll need to set the AC1 mode bit to a “0”.  AC1 for the first OLMC is fuse 2120.

Finally, there is a fuse that defines if the output is active high or active low (inverted).  The fuse for the first OLMC is 2048.

The OLMC configuration for simple mode is on page 9 of the specification at the link.

The JEDEC File

The TL866 programmer uses JEDEC files to define the fuses that will be set in the GAL device (.JED extension).  The fuse map portion of this file looks like this:

*L00000 00000000000000000000000000000000

*L00032 01011111111111111111111111111111

*L00064 00000000000000000000000000000000

*L00096 00000000000000000000000000000000

*L00128 00000000000000000000000000000000

*L00160 00000000000000000000000000000000

*L00192 00000000000000000000000000000000

*L00224 00000000000000000000000000000000

*L00256 11110111111111111111111111111111

*L00288 11110111111111111111111111111111

*L02048 00001111111111111111111111111111

*L02080 11111111111111111111111111111111

*L02112 11111111000000000100000011000000

*L02176 111111111111111110

The *L is the starting address of the line of fuses.  You can skip addresses that are not defined and they will become the default value as defined by the *F line in the file (zero being the default in this case).  As you can see L0000 through L00224 line up with the diagram of the circuit above.  One thing you’ll notice is that a “0” represents a fuse and a “1” is no fuse (that caused me a lot of frustration, when trying to reverse engineer this).

L02048 is the line that begins the XOR outputs (to define active low or active high).  Fuse 2056 through 2119 is a signature, so you can ignore these fuses.  Fuses 2120 through 2128 define the AC1 config parameter for the OLMC modules.  As mentioned earlier fuses 2128 through 2191 are the PTD fuses to define which AND gates will be turned off.  Finally the last two fuses are SYN and AC0.  You can see in the JEDEC file above that SYN and AC0 are set to 10.  That means that this GAL is setup for simple mode (each OLMC will behave in the simple configuration).  Here’s a list of fuses and their purpose in the GAL16V8 device:

0 - 2047 matrix

2048 XOR for OLMC 0 (0=active low [led lights], 1=active high)
2049 XOR for OLMC 1
2050 XOR for OLMC 2
2051 XOR for OLMC 3
2052 XOR for OLMC 4
2053 XOR for OLMC 5
2054 XOR for OLMC 6
2055 XOR for OLMC 7

2056 - 2119 Signature

2120 AC1 for OLMC 0
2121 AC1 for OLMC 1
2122 AC1 for OLMC 2
2123 AC1 for OLMC 3
2124 AC1 for OLMC 4
2125 AC1 for OLMC 5
2126 AC1 for OLMC 6
2127 AC1 for OLMC 7

2128 - 2191 PTD

2192 SYN
2193 AC0

There are other fields used in the JEDEC file.  Some are not used by the TL866.  One field in particular is the *C field, which is the checksum field.  The TL866 will compute this number and save it correctly, which is good because other software might blow up if the field is not right.  However, I have changed fuse patterns and not updated the *C field and the TL866 ignores it.  In the sample JEDEC file above, I also have fuses setup for the third input (pin 3).  This circuit will cause the second OLMC to output a “1” when pin 3 is a “1”.  You can download the file by clicking here and unzipping the zip file.  The specifications for the JEDEC file can be found here: PLD File Formats.

Where to Find GAL Devices

If you go to the on-line Jameco catalog and navigate to the semiconductor section, you’ll see a section called “Logic, Programmable“.  You’ll see a list of programmable chips.  There are some 16V8 devices as well as 22V10 and 20V8 devices.  I’m starting small and simple.  These things can get complicated in a hurry and it took a lot of re-programming to get it down.  The devices are about $2.25 each (as of this blog post) and Amazon has the TL866 programmer for around $50.  If you own the devices I listed in my last blog post on “Digital Electronics for the Beginner” you should have enough hardware to experiment with GAL devices.

If you have any specific questions about the GAL16V8 and how it’s programmed or the JEDEC file format, or if you know something about this device and think it should be appended to this blog post, please feel free to leave a comment.

 

Digital Electronics for the Beginner

Let’s say you’re a programmer and your experience in digital electronics involves that one class you were required to take in college.  Or…you’re a young person who is interested in learning this cool stuff, because, well… it seems cool.  One option is to buy one of those learning kits and go through the tutorials.  If you’re on a budget, you can start with one of these:

electronic_snap_circuitsI’ve played with this kit myself and I would recommend any parent that wants to introduce their kid to electronics, this is a good buy.  It has a card for each project that explains the circuit as well as the parts used by the circuit.  There are troubleshooting instructions and warnings about how to build a circuit without burning up components.

Let’s pretend that we wanted to just focus on some digital circuits and jump right into integrated circuits.  Here’s a list of what you’ll need to get started:

  1. Breadboard
  2. Power supply
  3. Wire
  4. IC assortment
  5. LEDs
  6. Resistors

Let’s start with the breadboard.  This is a large plastic “board” that has a lot of holes in it.  You use it to plug your wires, IC’s, LEDs and resistors into.  Integrated circuits are rather tiny, so attempting to wire them with alligator clips or twisting wire to the leads is not a good solution.  Radio Shack used to be my go-to place for stuff like breadboards, but they don’t sell much electronic stuff these days (assuming you can find a Radio Shack).  Jameco Electronics is my current go-to place to find anything I need.  Here’s a typical breadboard from Jameco (and a good starter one):

breadboardIf you’re on a really tight budget you can get one of the really small ones for under $5.00:

cheap_breadboardThe small breadboard above will probably fit 3 or 4 integrated circuits.  The Jameco brand one above will hold about 20 ICs.

Next, you’ll need a power supply.  I would recommend sticking to TTL logic circuits since they are more durable than any other integrated circuits (I’ll get to the details of this soon).  So you’ll need a stable 5v power supply to power your circuits.  This is probably the most expensive part.  If you’re comfortable with wiring a plug to a power supply you can go cheap and get something like this (for around $20):

cheap_power_supplyDon’t let the picture fool ya, it has a cover (you can see it in the spec sheet).  For a young adult, I would recommend spending more money and obtain a safer power supply, like this one:

power_supplyThis power supply has an adjustable output and costs around $67 at Amazon (click here).

I’m going to ignore the fact that you might need a meter to troubleshoot.  Technically, if you’re building TTL circuits, all you really need is a resistor and an LED.  So you can get a variety pack of resistors at Jameco for around $5 (click here):

resistor_assortmentFor a pack of LEDs, I would just by 10 of these, which are about 12 cents each (click here):

ledThe last boring component you’ll need is wire.  Just buy a roll of 22-guage solid wire.  Jameco has several colors available in 100 foot rolls for $8 (click here).

Now for the reason you’re doing this, the integrated circuits.  Jameco has some Grab Bags that are cheap, but they contain random TTL circuits and most are not very useful for an experimenter.  They also have component kits that contain known quantities of each type of TTL circuit, but those are really expensive.  So I would recommend buying this variety (filter to the 74LS series, they’re cheaper):

  • 2 inverters (74LS04)
  • 4 NAND gates (74LS00)
  • 2 NOR gates (74LS02)
  • 2 AND gates (74LS08)
  • 2 OR gates (74LS32)

The total for those should be under $6.

Let’s Build a Circuit

OK, you’re first circuit.  Let’s make this as easy as possible.  Here’s a circuit diagram of what we will build:

and_gate_circuit

Basically, it’s just an AND gate with both inputs set to zero and an LED output.  We will be switching our input wires to simulate a 1 or a 0 for inputs and see what the LED does.

Your first step is to install an AND gate (74LS08) into your breadboard.  To do this, you’ll need to identify pin 1.  There is usually a marking at one end of the chip and sometimes a small dot in the upper left corner.  The dot represents pin 1 and you should orient this chip on your breadboard with the dot facing up.  Here’s an example:

chip_insertedNotice how the IC straddles the groove in the breadboard.  The groove is a break in the contacts formed by the breadboard circuit.  Each line of holes run horizontally.  The numbers you see are the row numbers of each set of holes.  For line 30 (above), there are 5 holes in a horizontal row on the left and 5 holes on the right of the groove that are connected together.  For an in-depth explanation of how breadboards work, I would recommend reading this: How to use a breadboard.  Armed with this knowledge, I’ll continue with the circuit.

Next, you’ll need to go to your favorite search engine and find a tech sheet for the 7408 TTL circuit.  TTL can come in L, S, LS or normal package types.  The circuit number will always be “74” followed by an optional letter or pair of letters and then 2 or 3 digits like “08”.  So a 2-input AND gate can come in packages marked as 74LS08, 74L08, 74S08 or just 7408 (there are other types as well).  The package type is meaningless to this exercise so you can ignore which type of package you own (if you bought from the list above, you’ll have all “LS” type TTL circuits).  You can also ignore anything that comes before the “74”.  These characters represent the manufacturer.  So search the Internet for “TTL 7408” and you’ll stumble onto a PDF like this:

Quadruple 2-input Positive AND Gates

Now that your chip is properly inserted into the breadboard and you have a spec sheet, you’ll need to wire your power.  To form a complete circuit, each chip needs +5 volts and ground (or zero volts).  The spec sheet has a package diagram showing the pins of the chip:

ttl7408specYou’ll connect your +5 volts to the VCC pin (pin 14) and your ground or zero volts to the GND pin (pin 7).  Your breadboard should have some power runs along the side.  The Jameco board has red and blue stripes next to these power runs.  Connect your positive power supply to the red run and the ground to the blue run.  Then you can connect your chip like this:

power_connected

Next, you can connect an LED to the output.  First, let’s look at the spec sheet again and identify one AND gate that we can use.  If you examine the logic diagram you’ll see how the inputs and outputs of each AND gate is marked:

and_gate_logic_diagramThere are 4 AND gates on this chip, but we only need one.  So we’ll use the first one.  The first AND gate uses inputs 1A and 1B.  The output to this gate is 1Y.  In the pin-out diagram shown earlier, the inputs correspond to pins 1 and 2.  The output is on pin 3.  So let’s insert an LED and connect pin 3 to one side of the LED:

output_connected

LEDs are one-way devices, so when you insert the LED, make sure the long lead is connected to your wire.  If the circuit doesn’t work you can pull out the LED and reverse it.  Inserting an LED in backwards will not hurt anything.

The next step is very important because LEDs are sensitive to too much current.  So we’ll need a resistor to limit how much current is drawn by the LED.  If you don’t use a resistor you’ll hear a popping sound and you might smell something burning.  That would be the end of your LED.  If this happens, just throw it away, turn off your power, correctly wire a resistor (as I’ll describe next) and install a new LED.  As my high-school electronics professor used to say “no-burn, no-learn!”

On the short lead to your LED, connect one side of a 100 ohm resistor and connect the other side of the resistor to the blue bus bar (or ground).  To identify a 100 ohm resistor the colored stripes should be brown-black-brown (ignore the gold or silver stripe):

100_ohm_resistorResistors come in a variety of sizes.  To identify resistor sizes, you can go to this excellent website and memorize your color code (and it also includes a color code calculator).  Now your circuit should look something like this:

resistor_wired

Next, connect pins 1 and 2 to ground (or the blue bus):

circuit_done

Now, connect your power supply (plus lead connects to both red buses and the ground lead connects to both blue buses).  Adjust the voltage to +5 volts (if your power supply is adjustable).  Then turn it on… and… nothing happens.  This is the expected output.  So let’s make the LED light.  In order to do that, we’ll need to make both inputs a 1 or +5 volts.  Or do we?

TTL logic is wired in such a way that most circuits will treat an open input as a 1 or high.  So just remove the two input wires.  You can pull those wires while the circuit is on.  Notice how the LED lights up:

circuit_active

If your LED does not light, then you’ll need to troubleshoot.

  • Double-check to make sure all your wires are connected to the right pins.
  • You can see in the picture above that my IC is inserted between rows 56 to 62.  Row 56 on the right side is the positive connection.  Make sure the red bus on the right side is connected to the positive power supply lead.
  • Check the blue bus on the right side to make sure it is connected to ground.  Then check both the blue and red buses on the left, they will also need to be connected to the power supply.
  • Disconnect the wire from pin 3 of your AND gate and connect it right to the red bus.  Did the LED light up?  If not, then you need to check that the LED and resistor are wired correctly.  Maybe the LED is in backwards?
  • Make sure pin 14 (upper right) of your chip is wired to positive power and it is +5 volts.
  • Make sure pin 7 (lower left) is wired to ground (or the blue bus).
  • If the LED lights, but your circuit still doesn’t work, the chip could be bad (not likely, but you never know).  Turn off your power supply, remove the chip from the breadboard and insert another 74LS08 chip.  Make sure the pins are lined up exactly as the previous chip was lined up.

If your circuit is working, then you should experiment with all the combinations of inputs for your AND gate.  There are 4 possible inputs to a digital circuit that has two inputs.  Here’s a truth table of what the 4 inputs are for an AND gate:

and_gate_truth_tableAs you can see the circuit will only light if both inputs are a 1 or open.  If either input is a zero, then the light will go off.

The 74LS00 NAND gate can be substituted for your AND gate.  Make sure you turn off your power supply before removing one chip and inserting a new one.  Also be careful to line up the pins the same.

If you successfully tried the NAND gate, the NOR and OR gates are also identically pinned.  The inverter, however, is not.  So don’t attempt to wire the inputs and outputs the same because the inverter only has one input.  So pin 1 is the input and pin 2 is an output.  Feel free to connect the output of your 7404 to the LED (pin 2) and try pin 1 with high and low inputs.

Review

So what did we learn?

  • LEDs will burn out if we don’t limit the current they draw with a resistor.
  • LEDs go one way and the long lead is wired to the positive supply.
  • TTL chips are marked to identify pin 1.
  • TTL logic treats an open input as a 1 or a high.
  • We learned the resistor color code scheme.
  • We learned how to find and read a TTL IC spec sheet.
  • We learned how a breadboard works.
  • We learned how to wire power to a TTL chip.